1. Field of the Invention
The present invention relates to a synchronizing circuit applied to a sequence circuit etc. used in a large-scale integrated circuit etc.
2. Description of the Related Art
When realizing a logic circuit, in particular a sequence circuit which operates in synchronization with a clock such as an LSI circuit, a common design practice at the present time is to use a single-phase clock and delay type (D)-flipflops.
AS LSIs have become larger in scale, the delay time due to distribution of a clock signal has increased, and the use of frequency-divided clock signals and gated clock signals has led to deviations in timing of clock signals at ends of devices, that is, the clock skew has become greater, the possibility rises that the holding time of the D-flipflop will not be met and a malfunction will occur.
For example, in a 0.7 .mu.m rule CMOS, the maximum value of the clock skew is required to be on the order of 0.5 nsec. It is not easy to satisfy this requirement with a circuit of a size of over 100,000 gates.
Various attempts have been made, for example, tinkering with the clock interconnections, so as to overcome this disadvantage and to reduce the clock skew on the layout, as proposed in various references such as Baifukan, Ultrahigh Speed Digital Device Series 2, "Ultrahigh Speed MOS Devices", pp. 241 to 244"; Data Processing Society, 43rd (1991) National Conference (3R-8), "Clock Skew Minimization Interconnection Methods", Toshiba ULSI Institute; Data Processing Society, 43rd (1991) National Conference (3R-7), "Clock Skew Management Layout Methods", Oki Electric USLI Development Center; Shingaku Technical Reports IDC89-191, "0.8 .mu.m CMOS SOG With High Performance Clock Allocation Function", Mitsubishi Electric LSI Institute; NEC Technical Reports, Vol. 45, No. 8/1992, "Open CAD Clock Tree Synthesis", NEC ULSI System Development Institute).
The above-mentioned proposed circuits, however, still suffer from the following disadvantages.
When desiring to reuse an existing layout for each block, it is necessary to change the buffer configuration and cell deployment of the clock signal processing system to balance the chip as a whole, so in the final analysis in many cases the design has to be redone from the beginning.
Further, as processes become more advanced and the operating speed and number of gates increase, the requirements will become increasingly severe and there is a high possibility that they will not be able to be met.
In addition, other measures are necessary when using a frequency-divided clock signal or gated clock signal, which may be used in large-sized LSIs.
Further, basically, to overcome these advantages, the design technique has been known making use of a two-phase non-overlap clock signal and through latch as one full-custom design method, but the applications of this are limited due to the fact that two systems of clock signals are required and there are other troublesome facets of design or difficulty in verifying the maximum operating speed.
As shown in FIG. 1, even in a design using a single phase clock signal and D-flipflops DFF.sub.1 DFF.sub.3 . . . , a similar effect can be achieved. INV.sub.1 and INV.sub.2 show inverters comprising a clock input portion, and CIR shows a combination circuit arranged between the adjacent D-flipflops DFF. In this configuration, however, the number of D-flipflops ends up being doubled.
Further, as shown in FIG. 2, it is also effective if use is made of a single-phase clock signal and D-flipflops DFF.sub.4 and DFF.sub.5 and a delay gate comprised of the inverters INV.sub.3 to INV.sub.6 for example is inserted between the data output terminal Q of the D-flipflop DFF.sub.4 and the data input terminal D of the D-flipflop DFF.sub.5 or such a delay gate is created and attached to the D-flipflop DFF cell. In such a configuration, however, the number of gates or the cell area greatly increases.
Another disadvantage accompanying the increasing size of LSIs is the testing of the LSIs. Among the methods known for facilitating LSI tests, there is the scanning method of providing selectors before each input of the D-flipflop to construct a scanning circuit, as well as the cross check method of using lattice-like buried test circuits in the gate array. With these simplified test circuits, however, the additional test function causes the area of the D-flipflop to greatly increase.